This invention relates to a semiconductor dynamic memory device, and more particularly to an input stage receiving an external control signal to a semiconductor memory device having an internal refresh circuit.
A semiconductor dynamic memory device equipped with so-called "one-transistor dynamic memory cells" arrayed in matrix is widely used at present. The one-transistor dynamic memory cell consists of one insulated gate field effect transistor (IGFET) such as a MOS (Metal-Oxide-Semiconductor) transistor and one storage capacitor and is very simple in circuit configuration and device structure. Accordingly, a great number of memory cells is formed in a high integration, and thus a device having a large memory capacity is obtainable at a low cost. However, the data voltage stored in each memory cell is lowered due to the leakage current of the storage capacitor, and hence each row line (word line) of a memory cell array should be accessed periodically to restore the data in the memory cell. That is, a refresh operation is required.
The refresh operation may be effected by control signals externally supplied to the memory device. In the so-called "multi-address input type memory device" in which row and column address signals are supplied to the same address input terminals in synchronism with row and column address strobe (RAS and CAS) signals, each row line is selected in sequence by increasing (or decreasing) the content of the row address signals one by one in synchronism with the RAS signals, so that the memory cells connected to the selected row line are refreshed. Such a refresh operation is called as a "RAS" only refresh". However, since the row address signals are externally supplied to the memory device in synchronism with the RAS signal, an external control signal timing circuit becomes complicated.
In order to remove such a defect, a dynamic memory device provided with an internal refresh circuit has been developed. The internal refresh circuit carries out the refresh operation automatically at the time of a standby or the like. Such a memory device is often called as a "pseud-static memory device" and is widely employed.
The internal refresh circuit has a refresh timing circuit, an internal address counter and a timer circuit, and is controlled by a refresh signal supplied to a refresh (RFSH) terminal. An internal refresh mode is classified into a pulse-refresh mode and a self-refresh mode. When the refresh signal takes a refresh-enable level, the content of the internal address counter is supplied to a row decoder as a row address, so that one row line is selected by the row decoder to refresh the memory cells coupled to the selected row line. The content of the internal address counter is then increased (or decreased) by one. At this time, if the refresh signal is turned to a refresh-disenable level, the subsequent refresh operation is not be carried out. When the refresh signal takes the refresh-enable level again, the increased (or decreased) content of the internal address counter is supplied to the row decoder as a new row address, so that memory cells connected to the next row line are refreshed. The content of the internal refresh counter is then further increased (decreased) by one. Thus, the internal refresh operation is carried out every time the refresh signal takes the refresh-enable level. This is the pulse-refresh mode.
On the other hand, if the refresh signal is retained at the refresh-enable level, the timer circuit operates to generate a refresh request signal at every predetermined cycle periods. In response to the refresh request signal, the refresh timing circuit supplies the content of the internal address counter to the row decoder as a row address to refresh the memory cells, and the content of the internal address counter is then incremented (decremented) by one. As long as the refresh signal is retained at the refresh-enable level, the refresh request signal is generated, so that the row line is selected one by one to perform the refresh operation. This is the self-refresh mode.
A power consumption at a time when the internal refresh operation is carried out depends on the power consumed at an input stage connected to an input terminal (RAS terminal, for example) supplied with the external control signal, other than a current required for the refresh of the memory cells. A complementary MOS integrated circuit having P-channel and N-channel MOS transistors works on a low consumption power, and hence is employed in the memory device. A memory device using the complementary MOS structure has a complementary MOS inverter as the input stage for the purpose of the waveform-shaping of the external control signal. The complementary MOS inverter includes P-channel and N-channel MOS transistors connected in series between power supply terminals, and the gates thereof are connected in common to a signal input terminal, a signal supplied to an internal circuit being derived from the node thereof. When the input signal is in high a level, the N-channel MOS transistor is turned on, and the P-channel MOS transistor is cut off. When the input signal takes a low level, on the contrary, the P-channel MOS transistor is turned on, and the N-channel MOS transistor is turned off. Accordingly, the d.c. current flowing between the power supply terminals is slightly generated only when the conductive states of N-channel and P-channel MOS transistors are switched over, and hence a consumption power is satisfactorily small.
Particularly in the self refresh mode of the memory device, the row address strobe signal supplied to the RAS terminal is retained at an inactive level to prevent the external address signals from being supplied to the address input terminals. Consequently, each gate of the P-channel and N-channel MOS transistors in the input stage provided for the RAS terminal is subjected to the inactive level of the row address strobe signal throughout the self-refresh mode. If the inactive level is effective enough to turn either one of the P-channel and N-channel MOS transistors off, the power consumption in the input stage will scarcely occur. The external control signals are often generated through the TTL (Transistor-Transistor Logic) circuit to drive a plurality of memory devices. In such a case, the external control signals take an inactive level in the TTL level, so that such a level will turn both P-channel and N-channel MOS transistors on. Consequently, a d.c. current flows in the input stage during the period of the self-refresh mode, resulting in increase in the power consumption of the memory device.
Further, the row address strobe signal should be retained at the inactive level during the period of the self-refresh mode, and therefore the simplification of the external timing circuit cannot be satisfactory.